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ds07-12550-1e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89550a series MB89557A/558a/p558a/pv550a n n n n description the mb89550a series is a general-purpose, single-chip microcontroller that features a compact instruction set and contains a range of peripheral functions including a dual- clock control system, 5-level operating speed control, lcd controller driver, a/d converter, d/a converter, timer, serial interface, pwm timer, pwc timer, and external interrupts. the lcd controller driver is particularly suited for simultaneous control of lcd duty drive and static drive functions. n n n n features range of package options ? lqfp package (0.5 mm pitch) ? tqfp package (0.4 mm pitch) high speed operation at low voltage ? minimum instruction execution time 0.32 m s (for 12.5 mhz oscillation) f 2 mcr-8l cpu core instruction set optimized for controller applications ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test branch instructions ? bit manipulation instructions, etc. (continued) n n n n pac k ag e 100-pin plastic lqfp 100-pin plastic tqfp 100-pin ceramic mqfp (fpt-100p-m05) (fpt-100p-m18) (mqp-100c-p02)
mb89550a series 2 (continued) dual-clock control system ? main clock 12.5 mhz maximum : (four speed settings available, oscillation halts in sub-clock mode) ? sub-clock 32.768 khz : (operation clock for sub-clock mode) 11 timer systems ? 8/16-bit timer counter 1 (square wave output, 2-channel output switching available) ? 8/16-bit timer counter 2 (square wave output, 2-channel output switching available) ? 16-bit timer counter (also functions as event counter) ? 8-bit pwm timer (8-bit pwm timer 2 channels or ppg timer 1 channel, includes event counter function) ? 8-bit pwc timer (8-bit pwc timer 1 channel) ? 6-bit ppg timer (6-bit ppg timer 1 channel) ? 21-bit timebase timer ? clock prescaler (17-bit) uart/serial interface ? uart/sio switching uart ? clock synchronous/asynchronous switching available 10-bit a/d converter ? 10-bit a/d 8 channels 8-bit d/a converter ?8-bit d/a 2 channels external interrupts ? eight independent inputs can be used for recovery from low-power consumption modes (selection of rising, falling, or both edge detection functions). ? eight independent inputs can be used for recovery from low-power consumption modes (l level detection function included). clock output functions ? high speed clock signal multiplied by 2 available as output from hclk pin. ? low speed clock pulse output available from lclk pin. lcd controller driver ? 32seg 4com (maximum 128 pixels) 8 dedicated to segment output only 8 for port or segment use 16 for port, segment, or static use ? built-in step-up power supply for driving lcd (optionally available) low-power consumption modes (standby modes) ? stop mode (all oscillations halt in sub-clock mode, current consumption falls to almost zero) ? sleep mode (the cpu stops to reduce current consumption to approximately 1/3 of normal) ? clock mode (all operations other than the clock prescaler halt, current consumption is very low) ? sub clock mode (systems operate on sub-clock signals) maximum 66 i/o ports ? general-purpose i/o ports (n-ch open drain) : 4 ? general-purpose i/o ports (n-ch open drain) : 24 ? [also function as lcd ports, with restrictions] ? general purpose i/o ports (cmos) : 38
mb89550a series 3 n n n n product lineup * : the mb89pv550a provides only evaluation functions (functions for use with emulation tools). this model cannot use piggyback functions (functions for use with e 2 prom). part no. parameter mb89p558a-201 mb89p558a-202 mb89p558a-203 MB89557A mb89558a mb89pv550a*-201 mb89pv550a*-202 mb89pv550a*-203 rom size 48 kb 32 kb 48 kb ? ram size 2 kb 1 kb 2 kb 1 kb packages lqfp100 tqfp100 lqfp100 tqfp100 lqfp100 tqfp100 lqfp100 classification one-time product mask rom product mask rom product evaluation product cpu functions number of instructions : 136 instruction bit length : 8-bit instruction length : 1 to 3bytes data bit length : 1-, 8-, 16-bits minimum execution time : 0.32 m s (at 12.5 mhz) interrupt processing time : 2.88 m s (at 12.5 mhz) ports output-only ports (n-ch open drain) general-purpose i/o ports (n-ch open drain) general-purpose i/o ports (cmos) 8/16-bit timer counter 1 2-channel 8-bit timer/counter operation (also functions as 1-channel 16-bit timer) with square wave output function 8/16-bit timer counter 2 2-channel 8-bit timer/counter operation (also functions as 1-channel 16-bit timer) with square wave output function 16-bit timer counter 16-bit timer/counter operation, 16-bit event counter operation ppwm timer 2-channel 8-bit pwm timer operation (also functions as 1-channel ppg timer) with event counter function pwc timer 1-channel 8-bit pwc timer operation 6-bit ppg timer 1-channel 6-bit pwm timer operation lcd controller driver maximum 32seg?~4com (some ports provide selection of duty drive/static drive/n-ch open drain i/o port func- tions) uart sio switchable between uart (with clock synchronous/asynchronous data transfer function) and sio (simple serial) uart/sio data transfer function for uart/sio a/d converter 8-channel 10-bit resolution d/a converter 2-channel, 8-bit resolution clock output high speed clock multiplied 2, and sub clock output available standby modes sub clock mode, sleep mode, clock mode, and stop mode peripheral functions
mb89550a series 4 n n n n options and corresponding products *1 : the seg22-seg31 pins (n-ch open drain) are not subject to the restriction that input voltage (v in ) must be less than the voltage at the v3 pin. *2 : options may be specified at the time of mask rom ordering. n n n n oscillator stabilization wait time selection the MB89557A/558a allow a selection of default value for oscillator stabilization wait time, to be selected at the time of mask rom ordering. -201 options -202 options -203 options lcd step-up circuit no step-up circuit step-up circuit included port/seg dual-use pin selection seg8 to seg31 : seg/port dual use seg8 to seg31 : seg/port dual use seg8 to seg21 : seg/port dual use seg22 to seg31 : n-ch open drain* 1 model type evaluation model mb89pv550a-201 mb89pv550a-202 mb89pv550a-203 one-time model mb89p558a-201 mb89p558a-202 mb89p558a-203 mask rom model* 2 MB89557A MB89557A MB89557A mb89558a mb89558a mb89558a oscillator stabilization wait time selection remarks 2 14 /f ch 1.31 ms (at f = 12.5 mhz) 2 17 /f ch 10.48 ms (at f = 12.5 mhz) 2 18 /f ch 20.97 ms (at f = 12.5 mhz)
mb89550a series 5 n n n n differences among products and precautions for model selection package and model combinations note : compatible with all options (-201/202/203) . memory space ? when evaluating chips using piggyback evaluators etc., please take note of the differences among products before making the evaluation. current consumption ? when operating at low speed, one-time prom and eprom products will consume more current than mask rom products. however, the current consumption in sleep/stop modes is the same. ? for specific details about each package, see " n package dimensions". ? for details about power consumption, see " n electrical characteristics" . mask options ? the available options, and methods of using options, differ according to the model. be sure to confirm the options from the " n mask options" section. lcd drive step-up power circuit the mb89550a series is available with or without the step-up circuit option as a mask option. power supply path the models in the mb89550a series have two power supply pins, v cc1 and v cc2 , with power supply paths that differ according to the model. oscillator startup and power-on reset on the mb89pv550a and mb89p558a, oscillator startup and power-on reset are applied at the rise of the v cc2 input. on the mb89558a and MB89557A, oscillator startup and power-on reset are applied at the rise of the v cc1 input. models package mb89pv550a mb89p558a MB89557A mb89558a fpt-100p-m05 (lqfp-100 0.5 mm pitch) fpt-100p-m18 (tqfp-100 0.4 mm pitch) mqp-100c-p02 (mqfp-100 0.5 mm pitch) models supply pin power supply path MB89557A/ 558a v cc1 3v power supply pin for internal resource operation, including the cpu. v cc2 5v power supply pin for input/output ports. mb89p558a v cc1 v pp pin for on-board writing. v cc2 v power supply pin for internal resource operation, including the cpu, and for input/ output pins. mb89pv550a v cc1 internally shut off, operates as input to v cc2 only. v cc2 5v power supply pin for internal resource operation, including the cpu, and for input/ output pins.
mb89550a series 6 wide register functions the space available for use of wide register functions is as follows. the p40, p41, p84, p85 pins on the mb889pv550a, an external oscillator signal equivalent to 64 clock pulses is required to initialize the p40, p41, p84, and p85 pins. note therefore that at power-on there is an interval in which the values of these ports is undefined. on the mb89p558a, mb89558a, and MB89557A, these ports are set to "hi-z" status at power-on. mb89pv550a 2000 h to ffff h mb89p558a 4000 h to ffff h mb89558a 4000 h to ffff h MB89557A 8000 h to ffff h
mb89550a series 7 n n n n pin assignments (top view) (qfp-100) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 seg05 seg06 seg07 p50/seg08 v ss p51/seg09 p52/seg10 p53/seg11 p54/seg12 p55/seg13 p56/seg14 p57/seg15 p60/seg16 p61/seg17 p62/seg18 p63/seg19 p64/seg20 p65/seg21 p66/seg22 p67/seg23 p70/seg24 p71/seg25 p72/seg26 p73/seg27 p74/seg28 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p86/ec2/lclk p85/to22 p84/to21 dvr daout1 daout2 p31 p30 p27/int23 p26/int22 p25/int21 p24/int20 p23/ppg1 p22/uck p21/uo p20/ui p83/int27 p82/int26 p81/int25 v ss p80/int24 x1 x0 moda x1a 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p75/seg29 p76/seg30 p77/seg31 avr av cc p07/an7 p06/an6 p05/an5 p04/an4 p03/an3 p02/an2 p01/an1 p00/an0 av ss p17/int17 p16/int16 p15/int15 p14/int14 p13/int13 p12/int12 p11/int11 v cc 2 p10/int10 rst x0a 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 seg04 seg03 v cc 1 seg02 seg01 seg00 com3 com2 com1 com0 v3 v2 v1 v0 c0 c1 p47/pwc p46/si p45/so p44/sck p43/pwm2 p42/pwm1/ec1 p41/to12/hclk p40/to11/wto p87/ec3
mb89550a series 8 n n n n pin description (continued) pin no. pin name circuit type function 1 seg05 h segment output pins for lcdc duty drive. 2 seg06 h 3 seg07 h 4 p50/ seg08 g n-ch open drain i/o pin. also functions as a segment output pin for lcdc duty drive. 5v ss ? power supply (gnd) pin. 6 p51/ seg09 g n-ch open drain i/o pins. also function as segment output pins for lcdc duty drive. 7 p52/ seg10 8 p53/ seg11 9 p54/ seg12 10 p55/ seg13 11 p56/ seg14 12 p57/ seg15 13 p60/ seg16 g n-ch open drain i/o pins. also function as segment output pins for lcdc duty drive or static drive. 14 p61/ seg17 15 p62/ seg18 16 p63/ seg19 17 p64/ seg20 18 p65/ seg21 19 p66/ seg22 20 p67/ seg23 21 p70/ seg24 22 p71/ seg25
mb89550a series 9 (continued) pin no. pin name circuit type function 23 p72/ seg26 g n-ch open drain i/o pins. also function as segment output pins for lcdc duty drive or static drive. 24 p73/ seg27 25 p74/ seg28 26 p75/ seg29 27 p76/ seg30 28 p77/ seg31 29 avr ? a/d converter reference voltage input pin. 30 av cc ? a/d converter and d/a converter power supply pin. 31 p07/an7 d general purpose i/o ports. also function as analog input pins. 32 p06/an6 33 p05/an5 34 p04/an4 35 p03/an3 36 p02/an2 37 p01/an1 38 p00/an0 39 av ss ? a/d converter and d/a converter power supply pin (gnd). 40 p17/int17 e general purpose i/o ports. also function as external interrupt 1 input pins. external interrupt 1 input signals are hysteresis signals (edge detection). 41 p16/int16 42 p15/int15 43 p14/int14 44 p13/int13 45 p12/int12 46 p11/int11 47 v cc 2 ? power supply (5v) pin. 48 p10/int10 e general purpose i/o port. also functions as an external interrupt 1 input pin. external interrupt 1 input signals are hysteresis signals (edge detection). 49 rst i reset input pin. 50 x0a a crystal oscillator pins (32 khz) . 51 x1a
mb89550a series 10 (continued) pin no. pin name circuit type function 52 moda f operating mode setting pin. 53 x0 a crystal oscillator pins (max12.5 mhz) . 54 x1 55 p80/int24 e general purpose i/o port. also functions as an external interrupt 2 input pin. external interrupt 2 input signals are hysteresis signals (level detection). 56 v ss ? power supply (gnd) pin. 57 p81/int25 e general purpose i/o ports. also function as external interrupt 2 input pins. external interrupt 2 input signals are hysteresis signals (level detection). 58 p82/int26 59 p83/int27 60 p20/ui e general purpose i/o ports. also function as 8-bit serial i/o pins. 61 p21/uo b 62 p22/uck e 63 p23/ppg1 b general purpose i/o port. also functions as the 6-bit ppg timer output. 64 p24/int20 e general purpose i/o ports. also function as external interrupt 2 input pins. external interrupt 2 input signals are hysteresis signals (level detection). 65 p25/int21 66 p26/int22 67 p27/int23 68 p30 k n-ch open drain i/o pins. 69 p31 70 daout2 c d/a converter output pins. 71 daout1 72 dvr ? d/a converter reference voltage input pin. 73 p84/to21 b general purpose i/o ports. also function as 8/16-bit timer pins. p84 can be used as the output for the main clock 2 pulse. p86 can be used as the event counter input or sub-clock pulse output. 74 p85/to22 75 p86/ec2/ lclk e 76 p87/ec3 e general purpose i/o port. also functions as a 16-bit timer pin. 77 p40/to11/ wto b general purpose i/o ports. also function as 8/16-bit timer pins. 78 p41/to12/ hclk 79 p42/ pwm1/ ec1 e general purpose i/o ports. also function as pwm timer pins. 80 p43/pwm2 b
mb89550a series 11 (continued) pin no. pin name circuit type function 81 p44/sck e general purpose i/o ports. also function as uart pins. 82 p45/so b 83 p46/si j 84 p47/pwc j general purpose i/o port. also functions as the pwc timer pin. 85 c1 ? step-up voltage circuit capacitance connection pins. 86 c0 87 v0 ? lcd drive power supply pins. 88 v1 89 v2 90 v3 91 com0 h dedicated lcdc common output pins. 92 com1 93 com2 94 com3 95 seg00 h dedicated lcdc segment output pins. 96 seg01 97 seg02 98 v cc 1 ? power supply (3v) pin. 99 seg03 h dedicated lcdc segment output pins. 100 seg04
mb89550a series 12 n n n n i/o circuit types (continued) type circuit remarks a oscillation feedback resistance ? high speed side = approx. 1 m w ? low speed side = approx. 4.5 m w b ?cmos i/o c ? d/a output d ? a/d input ?cmos i/o x1 (x1a) x0 (x0a) main clock control signal (sub-clock control signal) pch pch nch r pull-up control register input control signal output enable analog output pch pch nch r pull-up control register analog input port input input control signal
mb89550a series 13 (continued) type circuit remarks e ?cmos i/o ? hysteresis input (for external inter- rupt 0, 1, 2 input) f ? cmos input g ? lcdc output ? n-ch open drain i/o h ? lcdc output i ? hysteresis input ? pull-up resistance j ? hysteresis input ? n-ch open drain i/o pch pch nch r pull-up control register port input resource input input control signal input nch input control signal port input r pch nch input nch resource input port input input control signal
mb89550a series 14 (continued) type circuit remarks k ? n-ch open drain i/o nch port input input control signal
mb89550a series 15 n n n n handling devices ? maximum rated voltage (prevention of latchup) be careful never to exceed maximum rated voltages. in cmos ic devices, a condition known as latch-up may occur if voltages higher than vcc or loser than vss are applied to input or output pins other than medium- or high-voltage pins, or if the voltage applied between vcc and vss exceeds the rated voltage level. when latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (avcc, avr, and dvr) and analog input voltages do not exceed the digital power supply (vcc). ? power supply voltages power supply voltages should be kept as stable as possible. rapid fluctuation of the voltage may cause the device to operate abnormally, even if the voltage remains within the allowed operating range. as a standard for power supply voltage stability, it is recommended that the peak-to-peak vcc ripple voltage at commercial supply frequency (50 hz to 60 hz) be 10% or less of vcc. also when the power supply is turned on or off the transient voltage fluctuation be no more than 0.1v/ms or less. ? treatment of unused input pins leaving unused input pins unconnected can cause abnormal operation. unused input pins should always be pulled up or down. ? treatment of n.c. pins n.c. (not connected) pins should always be left open. ? treatment of power supply pins on devices with a/d or d/a converters even when the a/d or d/a converters are not in use, be sure to make the necessary connections to ensure that av cc = v cc , av ss = avr = dvr = v ss . ? precautions on using an external clock an oscillation stabilization delay occurs after a power-on reset or when recovering from sub-clock or stop mode, even if an external clock is used. ? treatment of unused dedicated lcd pins dedicated seg output pins should be left open when not in use. ? handling of ports also used as segment pins when a ports is used as a segment pin, take care to ensure that the voltage applied to the pin does not exceed v3 (the segment drive voltage). this precaution is particularly necessary in models with step-up voltage circuits. note also that after power-on or during a reset, an l level default signal is output form the segment/port pin. ? treatment of unused lcd pins connect the v3 pin to v cc2 . the other dedicated lcd pins v0, v1, v2, c0, and c1 should be pulled down. ? executing programs on ram when programs are executed on ram, debugging cannot be performed even with the use of the mb89pv550a. ? wild register functions wild registers cannot be debugged with the mb89pv550a or tools. to verify operation, use the mb89p558a and perform in-place testing.
mb89550a series 16 n n n n programming specifications for one-time prom products the mb89p558a has a "prom mode" with functions equivalent to the mbm27c1001, that enables the micro- controller to be programmed by writing from a general-purpose rom programmer with the use of a special adapter. note however that electronic signature mode is not available. rom programmer adapters with some rom programmers the insertion of approximately 0.1 m f capacitance between v pp and v ss or between v cc and v ss allows more stable writing performance. the following table lists rom programmer adapters. rom programmer adapters ? inquiries sun hayato co., ltd. : tel 03-3986-0403 ? prom mode memory map the prom mode memory map is shown below. prom mode memory map part no. package adapter part no. mb89p558a fpt-100p-m05 rom-100sqf-32dp-8la2 fpt-100p-m18 rom-100sqf-32dp-8la 14000 h 1ffff h 0000 h ram i/o 0080 h ffff h 4000 h 0880 h normal operating mode not availablel prom mode (addresses on rom programmer) program area ( prom ) program area (prom)
mb89550a series 17 ? eprom programming procedure 1) set the eprom programmer type to mbm27c1001. 2) load the program data into addresses 14000 h to 1ffff h in the eprom programmer. 3) use the eprom programmer to program to addresses 14000 h to 1ffff h . ? recommended screening conditions high-temperature aging is the recommended method of screening unprogrammed one-time prom microcon- trollers before mounting. the flow of the screening process is shown below. screening flow ? about writing yields the nature of chips before one-time writing of microcontroller programs to prom prevents the use of all-bit writing tests. therefore it is not possible to guarantee writing yields of 100 % in some cases. program, verify high-temperature aging + 150 c, 48 h read mount
mb89550a series 18 n n n n block diagram x0 x1 x0a x1a rst v3 ~ v0 c1 , c0 p77/seg31 ~ p70/seg24 p67/seg23 ~ p60/seg16 p57/seg15 ~ p50/seg08 p83/int27 ~ p80/int24 p27/int23 ~ p24/int20 p17/int17 ~ p10/int10 seg07 ~ seg00 com3 ~ com0 cmos i/o port ram 1 k/2 kbyte f2mc-8l cpu rom 32 k/48 kbyte v ss v ss v cc 1v cc 2 moda p43/pwm2 p42/pwm1/ec1 p41/to12/hclk p40/to11/wto p85/to22 p84/to21 p86/ec2/lclk p87/ec3 p23/ppg1 p20/ui p21/uo p22/uck p44/sck p45/so p46/si p47/pwc daout1 daout2 dvr av cc av ss avr p30 p31 p00/an0 ~ p07/an7 6 bit ppg uart/sio uart sio cmos i/o port cmos i/o port main clock oscillator circuit & sub-clock oscillator circuit clock control circuit reset output circuit power-on reset & wdg circuit lcd display power genera- tion and step- up circuit lcd controller & driver control circuit static drive control circuit external inter- rupt 2 (level) wild register circuit 6 byte other pins 8-bit timer counter clock output 16-bit timer counter 8-bit pwc timer n-ch od i/o ports 2-channel 8-bit d/a converter 8-channel 10-bit a/d converter internal bus lcd driver & n-ch od i/o ports external inter- rupt 1 (edge) 8-bit timer counter 8-bit timer counter 8-bit timer counter 2-channel 8-bit pwm timer 21-bit time base timer n-ch open drain i/o ports
mb89550a series 19 n n n n cpu core memory space the mb89550a has 64 kbytes of memory space, composed of the i/o area, ram area, rom area, and external area. the memory space includes general purpose registers, as well as areas used for special purposes such as vector tables. i/o area (address : 0000 h to 007f h ) ? this area is allocated to control registers and data registers for internal peripheral functions. ? because the i/o area is part of memory space, it can be accessed in the same ways. direct addressing provides faster access. ram area ? static ram is provided for use as an internal data area. ? the size of internal ram differs between product models. ? high speed access is available to addresses 80 h to ff h using direct addressing (the area available for use is restricted on some models). ? addresses 100 h to 1ff h are used as the general-purpose register area. ? if a reset is applied during writing to ram, the value of date at the target addresses is not assured. rom area ? rom is provided for use as the internal program area. ? the size of internal rom differs between product models. ? addresses ffc0 h to ffff h are used for special purpose data such as vector tables. memory map 0000 h ram rom rom i/o 0080 h 0492 h 0480 h ffff h 0200 h 0100 h 8000 h ffc0 h 0000 h ram MB89557A mb89p558a mb89558a ram i/o 0080 h 0492 h 0480 h ffff h 0200 h 0100 h 0880 h 4000 h ffc0 h 0000 h ram mb89pv550a i/o 0080 h 0492 h 0480 h ffff h 0200 h 0100 h 4000 h ffc0 h register wild register not available vector tables (reset, interrupt, vector call instructions) register wild register register wild register not available not available external rom vector tables (reset, interrupt, vector call instructions) vector tables (reset, interrupt, vector call instructions)
mb89550a series 20 n n n n i/o map (continued) address abbreviation resister name read/write initial value 00 h pdr0 port 0 data register r/w xxxxxxxx b 01 h ddr0 port 0 direction register w 0 0 0 0 0 0 0 0 b 02 h pdr1 port 1 data register r/w xxxxxxxx b 03 h ddr1 port 1 direction register w 0 0 0 0 0 0 0 0 b 04 h to 06 h unused area 07 h sycc system clock control register r/w xxx mm1 0 0 b 08 h stbc standby control register r/w 0 0 0 1 0 xxx b 09 h wdtc watchdog control register r/w 0xxxxxxx b 0a h tbtc time base time control register r/w x 0 xxx 0 0 0 b 0b h wpcr clock prescaler control register r/w x 0 xx 0 0 0 0 b 0c h pdr2 port 2 data register r/w xxxxxxxx b 0d h ddr2 port 2 direction register r/w 0 0 0 0 0 0 0 0 b 0e h pdr3 port 3 data register r/w - - - - - - 1 1 b 0f h pdr4 port 4 data register r/w 1 1 xxxxxx b 10 h ddr4 port 4 direction register r/w - - 0 0 0 0 0 0 b 11 h pdr5 port 5 data register r/w 0 0 0 0 0 0 0 0 b 12 h unused area 13 h pdr6 port 6 data register r/w 0 0 0 0 0 0 0 0 b 14 h unused area 15 h pdr7 port 7 data register r/w 0 0 0 0 0 0 0 0 b 16 h unused area 17 h pdr8 port 8 data register r/w xxxxxxxx b 18 h ddr8 port 8 direction register r/w 0 0 0 0 0 0 0 0 b 19 h unused area 1a h t2cr#2 timer 2 control register # 2(8/16-bit timer/counter -1) r/w x 0 0 0 0 0 x 0 b 1b h t1cr#1 timer 1 control register # 1(8/16-bit timer/counter -1) r/w x 0 0 0 0 0 x 0 b 1c h t2dr#2 timer 2 data register # 2(8/16-bit timer/counter -1) r/w xxxxxxxx b 1d h t1dr#1 timer 1 data register # 1(8/16-bit timer/counter -1) r/w xxxxxxxx b 1e h t2cr#4 timer 2 control register # 4(8/16-bit timer/counter -2) r/w x 0 0 0 0 0 x 0 b 1f h t1cr#3 timer 1 control register # 3(8/16-bit timer/counter -2) r/w x 0 0 0 0 0 x 0 b 20 h t2dr#4 timer 2 data register # 4(8/16-bit timer/counter -2) r/w xxxxxxxx b 21 h t1dr#3 timer 1 data register # 3(8/16-bit timer/counter -2) r/w xxxxxxxx b 22 h smc1 serial mode control register 1 (uart) r/w 0 0 0 0 0 0 0 0 b 23 h src1 serial rate control register (uart) r/w - - 0 1 1 0 0 0 b
mb89550a series 21 (continued) address abbreviation resister name read/write initial value 24 h ssd1 serial status and data register (uart) r/w 0 0 1 0 0 - 1x b 25 h sidr1/ sodr1 serial input/serial output data register (uart) r/w xxxxxxxx b 26 h smc2 serial mode control register 2 (uart) r/w - - 1 0 0 0 0 1 b 27 h cntr1 pwm control register 1 r/w 0 0 0 0 0 0 0 0 b 28 h cntr2 pwm control register 2 r/w 0 0 0 x 0 0 0 0 b 29 h cntr3 pwm control register 3 r/w x 0 0 0 xxxx b 2a h comr1 pwm compare register 1 w xxxxxxxx b 2b h comr2 pwm compare register 2 w xxxxxxxx b 2c h pcr1 pwc pulse width control register 1 r/w 0 0 0 xx 0 0 0 b 2d h pcr2 pwc pulse width control register 2 r/w 0 0 0 0 0 0 0 0 b 2e h plbr pwc reload buffer register r/w xxxxxxxx b 2f h smc21 serial mode control register 1 (uart/sio) r/w 0 0 0 0 0 0 0 0 b 30 h smc22 serial rate control register 2 (uart/sio) r/w 0 0 0 0 0 0 0 0 b 31 h ssd2 serial status and data register (uart/sio) r/w 0 0 0 0 1 xxx b 32 h sidr2/ sodr2 serial input/serial output date register (uart/sio) r/w xxxxxxxx b 33 h src2 baud rate generator reload register (uart/sio) r/w xxxxxxxx b 34 h adc1 a/d control register 1 r/w 0 0 0 0 0 0 0 0 b 35 h adc2 a/d control register 2 r/w x 0 0 0 0 0 0 1 b 36 h addl a/d data register low r/w xxxxxxxx b 37 h addh a/d data register high r/w 0 0 0 0 0 0 xx b 38 h to 3b h unused area 3c h tmcr timer control register (16-bit timer/counter) r/w xx 0 0 0 0 0 0 b 3d h tchr timer count register high (16-bit timer/counter) r/w 0 0 0 0 0 0 0 0 b 3e h tclr timer count register low (16-bit timer/counter) r/w 0 0 0 0 0 0 0 0 b 3f h eic1 external interrupt register 1 r/w 0 0 0 0 0 0 0 0 b 40 h eic2 external interrupt register 2 r/w 0 0 0 0 0 0 0 0 b 41 h eic3 external interrupt register 3 r/w 0 0 0 0 0 0 0 0 b 42 h eic4 external interrupt register 4 r/w 0 0 0 0 0 0 0 0 b 43 h dacr d/a control register r/w xxxxxx 0 0 b 44 h dadr1 d/a data register 1 r/w xxxxxxxx b 45 h dadr2 d/a data register 2 r/w xxxxxxxx b 46 h to 55 h unused area 56 h eie2 external interrupt 2 control register r/w 0 0 0 0 0 0 0 0 b
mb89550a series 22 (continued) address abbreviation resister name read/write initial value 57 h eif2 external interrupt 2 flag register r/w xxxxxxx 0 b 58 h rcr1 6-bit ppg control register 1 r/w 0 0 0 0 0 0 0 0 b 59 h rcr2 6-bit ppg control register 2 r/w 0 - 0 0 0 0 0 0 b 5a h ckr clock output control register r/w xxxxxx 0 0 b 5b h lcr1 lcdc control register 1 r/w 0 0 0 1 0 0 0 0 b 5c h lcr2 lcdc control register 2 r/w 0 0 0 0 0 0 0 0 b 5d h lcr3 lcdc control register 3 r/w - - - 0 0 0 0 0 b 5e h lcd1 lcd static display register 1 r/w xxxxxxxx b 5f h lcd2 lcd static display register 2 r/w xxxxxxxx b 60 h to 6f h vram lcd display ram r/w xxxxxxxx b 70 h smr serial mode register (8-bit serial i/o) r/w 0 0 0 0 0 0 0 0 b 71 h sdr serial data register (8-bit serial i/o) r/w xxxxxxxx b 72 h porr0 port 0 pull-up option setting register r/w 1 1 1 1 1 1 1 1 b 73 h purr1 port 1 pull-up option setting register r/w 1 1 1 1 1 1 1 1 b 74 h purr2 port 2 pull-up option setting register r/w 1 1 1 1 1 1 1 1 b 75 h purr4 port 4 pull-up option setting register r/w 1 1 1 1 1 1 1 1 b 76 h purr8 port 8 pull-up option setting register r/w 1 1 1 1 1 1 1 1 b 77 h wren wild register/address comparator enable register r/w - - 0 0 0 0 0 0 b 78 h unused area 79 h aden a/d port input enable register r/w 1 1 1 1 1 1 1 1 b 7a h unused area 7b h ilr1 interrupt level setting register 1 w 1 1 1 1 1 1 1 1 b 7c h ilr2 interrupt level setting register 2 w 1 1 1 1 1 1 1 1 b 7d h ilr3 interrupt level setting register 3 w 1 1 1 1 1 1 1 1 b 7e h ilr4 interrupt level setting register 4 w 1 1 1 1 1 1 1 1 b 7f h unused area
mb89550a series 23 extended i/o area o read/write notation o initial value notation note : areas indicated as "unused area" are not to be used. address abbreviation resister name read/write initial value 480 h wrarh1 h address setting register 1 r/w xxxxxxxx 481 h wrarl1 l address setting register 1 r/w xxxxxxxx 482 h wrdr1 data setting register 1 w xxxxxxxx 483 h wrarh2 h address setting register 2 r/w xxxxxxxx 484 h wrarl2 l address setting register 2 r/w xxxxxxxx 485 h wrdr2 data setting register 2 w xxxxxxxx 486 h wrarh3 h address setting register 3 r/w xxxxxxxx 487 h wrarl3 l address setting register 3 r/w xxxxxxxx 488 h wrdr3 data setting register 3 w xxxxxxxx 489 h wrarh4 h address setting register 4 r/w xxxxxxxx 48a h wrarl4 l address setting register 4 r/w xxxxxxxx 48b h wrdr4 data setting register 4 w xxxxxxxx 48c h wrarh5 h address setting register 5 r/w xxxxxxxx 48d h wrarl5 l address setting register 5 r/w xxxxxxxx 48e h wrdr5 data setting register 5 w xxxxxxxx 48f h wrarh6 h address setting register 6 r/w xxxxxxxx 490 h wrarl6 l address setting register 6 r/w xxxxxxxx 491 h wrdr6 data setting register 6 w xxxxxxxx r/w : reading and writing enabled r : read-only w : write only 0 : initial value of bit is 0. 1 : initial value of bit is 1. x : initial value of bit is undefined.
mb89550a series 24 n n n n electrical characteristics 1. absolute maximum ratings (avss = vss = 0 v) (continued) parameter symbol rating unit remarks min max power supply voltage v cc1 v ss - 0.3 v ss + 4.0 v v cc1 not to exceed v cc2 .* v cc2 v ss - 0.3 v ss + 6.0 a/d converter reference input voltage avr v ss - 0.3 v ss + 6.0 v d/a converter reference input voltage dvr v ss - 0.3 v ss + 6.0 v lcd power supply voltage v0-v3 v ss - 0.3 v ss + 6.0 v on models without step-up circuits v0-v3 are not to exceed v cc2 . input voltage v i1 v ss - 0.3 v cc 2 + 0.3 v pins other than p50 to p57, p60 to p67, p70 to p77, p46, p47, p30, p31 v i2 v ss - 0.3 v3 v p50 to p57, p60 to p67, p70 to p77 v i3 v ss - 0.3 v ss + 6.0 v p46, p47, p30, p31 output voltage v o1 v ss - 0.3 v cc 2v pins other than p50 to p57, p60 to p67, p70 to p77, p46, p47, p30, p31 v o2 v ss - 0.3 v3 v p50 to p57, p60 to p67, p70 to p77 v o3 v ss - 0.3 v ss + 6.0 v p46, p47, p30, p31 l level maximum output current i ol1 ? 15 ma pins other than p22/uck, p23/ ppg1 i ol2 ? 30 ma p22/uck, p23/ppg1 l level average output current i olav1 ? 4ma pins other than p22/uck, p23/ ppg1 average value (operating current operating ratio) i olav2 ? 15 ma p22/uck, p23/ppg1 average value (operating current operating ratio) l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 60 ma average value (operating current operating ratio) h level maximum output current i oh1 ?- 15 ma pins other than p22/uck, p23/ ppg1 i oh2 ?- 30 ma p22/uck, p23/ppg1
mb89550a series 25 (continued) * : set av cc to the same potential as v cc . also ensure that avr and dvr do not exceed av cc + 0.3 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max h level average output current i ohav ?- 4ma pins other than p22/uck, p23/ ppg1 and open drain output pins average value (operating current operating ratio) i ohav ?- 15 ma p22/uck, p23/ppg1 average value (operating current operating ratio) h level total maximum output current s i oh ?- 50 ma h level total average output current s i ohav ?- 30 ma average value (operating current operating ratio) power consumption p d ? 300 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c
mb89550a series 26 2. recommended operating conditions (avss = vss = 0 v) *1 : the operating power supply voltage differs depending on the instruction cycle time of the operating frequency. see figure 1. *2 : the operating power supply voltage differs depending on the instruction cycle time of the operating frequency. see figure 2. note also that on the mb89pv550a the input to the v cc1 pin is cut off internally, and on the mb89p558a the v cc1 pin is used as the v pp pin for on-board writing. *3 : avcc and v cc2 should be set to the same potential. also, care must be taken to ensure that v cc1 does not exceed v cc2 . *4 : care must be taken to ensure that the relation between avr and dvr is such that v cc1 avr (dvr) av cc + 0.3 v. item symbol rating unit remark min max power supply voltage* 3 v cc1 2.2* 1 3.6 v guaranteed normal operating range (MB89557A/558a) v cc2 2.2* 1 5.5 v v cc1 ?? v guaranteed normal operating range (mb89p558a) v cc2 2.7* 2 5.5 v v cc1 , v cc2 1.5 3.6 v to maintain ram state in stop mode a/d converter reference voltage input* 4 avr v cc1 av cc v guaranteed normal operating range d/a converter reference voltage input* 4 dvr v cc1 av cc v guaranteed normal operating range lcd supply voltage v0-v3 v ss v cc2 v models without step-up circuit, pins v0 to v3. lcd power supply range and maximum value are determined by the characteristics of the lcd display ele- ment used. operating temperature t a - 40 + 85 c
mb89550a series 27 figure 1. operating voltage vs. operating frequency (mb89558a/557a) figure 2. operating voltage vs. operating frequency (mb89p558a) 6 5 4 3 2 1 6 5 4 3 2 1 1.0 4.0 2.0 2.0 3.0 4.0 5.0 0.8 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 0.32 0.4 MB89557A/mb89558a * : t a = - 40 c ~ +85 c * : analog precision warranted range : av cc = 3.5 v to 5.5 v operating voltage (v cc 1) operating frequency (mhz) (at instruction cycle = 4 / fc) instruction cycle ( m s) 6 5 4 3 2 1 6 5 4 3 2 1 1.0 4.0 2.0 2.0 3.0 4.0 5.0 0.8 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 0.32 0.4 mb89p558a * : t a = - 40 c ~ +85 c : t a = - 10 c ~ +55 c : t a = + 25 c * : v cc 2 = 2.2 v to 5.5 v (v cc 2 3 v cc 1) analog precision warranted range : av cc = 3.5 v to 5.5 v instruction cycle ( m s) operating frequency (mhz) (at instruction cycle = 4 / fc) operating voltage (v cc 2)
mb89550a series 28 warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand.
mb89550a series 29 3. dc characteristics (av cc = avr = dvr = v cc2 = 5.0 v, avss = vss = 0 v, t a = - 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max h level input voltage v ih1 p00 to p07, p10 to p17, p20 to p27, p40 to p45, p80 to p87 ? 0.7 v cc2 ? v cc2 + 0.3 v v ih2 p50 to p57, p60 to p67, p70 to p77 ? 0.7 v cc2 ? v3 v v ih2 not to exceed v3. v ih3 p46, p47, p30, p31 ? 0.7 v cc2 ? v ss + 5.5 v v ihs1 int10 to int17 , ui, uck, int20 to int27 , sck, ec1, ec2, ec3, rst , moda ? 0.8 v cc2 ? v cc2 + 0.3 v hysteresis input v ihs2 si, pwc ? 0.8 v cc2 ? v ss + 5.5 v hysteresis input l level input voltage v il1 p00 to p07, p10 to p17, p20 to p27, p30, p31, p40 to p47, p80 to p87 ? v ss - 0.3 ? 0.3 v cc2 v v il2 p50 to p57, p60 to p67, p70 to p77 ? v ss - 0.3 ? 0.3 v cc2 v v il2 not to exceed v3. v ils int 10 to int 17, ui, uck, int20 to int27 , sck, ec1, ec2, ec3, rst , moda, si, pwc ? v ss - 0.3 ? 0.2 v cc2 v hysteresis input voltage applied to open drain output pins v d1 p46, p47, p30, p31 ? v ss - 0.3 ? v ss + 5.5 v v d2 p50 to p57, p60 to p67, p70 to p77 ? v ss - 0.3 ? v3 v v d2 not to exceed v3. h level output voltage v oh1 p00 to p07, p10 to p17, p20, p21, p24 to p27, p40 to p45, p80 to p87 i oh = - 2.0 ma 4.0 ?? v v oh2 p22, p23 i oh = - 4.0 ma 4.0 ?? v l level output voltage v ol1 p00 to p07, p10 to p17, p20, p21, p24 to p27, p30, p31, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87 i ol = 4.0 ma ?? 0.4 v v ol2 p22, p23 i ol = 12 ma ?? 0.4 v input leak current (hi-z output leak current) i li p00 to p07, p10 to p17, p20 to p27, p30, p31 p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, moda 0.0v < v i < v cc2 ?? 5 m a without pull-up resistor option
mb89550a series 30 (av cc = avr = dvr = v cc2 = 5.0 v, avss = vss = 0 v, t a = - 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max pull-up resistance r pull p00 to p07, p10 to p17, p20 to p27, p40 to p45, p80 to p87, rst v i = 0.0 v 25 50 100 k w with pull-up resistor option power supply current i cc1 v cc1 v cc1 = 3.0 v v cc2 = 5.0 v f ch = 12.5 mhz ? 4.5 6 ma t inst = 0.32 m s MB89557A/ 558a v cc2 v cc2 = 5.0 v f ch = 12.5 mhz ? 22 25 ma t inst = 0.32 m s mb89p558a i cc2 v cc1 v cc1 = 3.0 v v cc2 = 5.0 v f ch = 10.0 mhz ? 1.4 2.1 ma t inst = 6.4 m s MB89557A/ 558a v cc2 v cc2 = 3.0 v f ch = 10.0 mhz ? 5.3 9 ma t inst = 6.4 m s mb89p558a i ccs1 v cc1 v cc1 = 3.0 v v cc2 = 3.0 v f ch = 12.5 mhz ? 23ma sleep mode t inst = 0.32 m s MB89557A/ 558a v cc2 v cc2 = 5.0 v f ch = 12.5 mhz ? 6.2 10 ma sleep mode t inst = 0.32 m s mb89p558a i ccs2 v cc1 v cc1 = 3.0 v v cc2 = 3.0 v f ch = 10.0 mhz ? 0.35 1 ma sleep mode t inst = 6.4 m s MB89557A/ 558a v cc2 v cc2 = 3.0 v f ch = 10.0 hz ? 0.6 2 ma sleep mode t inst = 6.4 m s mb89p558a i ccl v cc1 v cc1 = 3.0 v v cc2 = 5.0 v f cl = 32 khz t a = + 25 c ? 30 50 m a sub-mode MB89557A/ 558a v cc2 v cc2 = 3.0 v f cl = 32 khz t a = + 25 c ? 48ma sub-mode mb89p558a i ccls v cc1 v cc1 = 3.0 v v cc2 = 3.0 v f cl = 32 khz t a = + 25 c ? 10 20 m a sub-sleep mode MB89557A/ 558a v cc2 v cc2 = 3.0 v f cl = 32 khz t a = + 25 c ? 20 50 m a sub-sleep mode mb89p558a
mb89550a series 31 (av cc = avr = dvr = v cc2 = 5.0 v, avss = vss = 0 v, t a = - 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max power supply current i cct v cc1 v cc1 = 3.0 v v cc2 = 3.0 v t a = + 25 c f cl = 32 khz ? 515 m a clock mode main stop MB89557A/ 558a v cc2 v cc2 = 3.0 v f cl = 32 khz t a = + 25 c ? 12 25 m a clock mode main stop mb89p558a i cch v cc1 v cc1 = 3.0 v v cc2 = 3.0 v f cl = 32 khz t a = + 25 c ? 510 m a t a = + 25 c sub- stop MB89557A/ 558a v cc2 v cc2 = 3.0 v f cl = 32 khz t a = + 25 c ? 510 m a t a = + 25 c sub- stop mb89p558a i a av cc v cc1 = 3.0 v av cc = v cc2 = 5.0 v f ch = 12.5 mhz ? 25ma a/d converter running MB89557A/ 558a av cc v cc2 = 5.0 v f ch = 12.5 mhz ? 36ma a/d converter running mb89p558a i ah av cc v cc1 = 3.0 v, av cc = v cc2 = 5.0 v f ch = 12.5 mhz t a = + 25 c ?? 10 m a t a = + 25 c a/d converter stopped MB89557A/ 558a av cc v cc2 = 5.0 v f ch = 12.5 mhz t a = + 25 c ?? 10 m a t a = + 25 c a/d converter stopped mb89p558a lcd divider resistance r lcd ? v cc to v 0 at v cc = 5 v ? 500 ? k w com0 to com3 output impedance r vcom com0 to com3 v1 to v3 = 5 v ?? 5k w seg0 to seg31 output impedance r vseg seg0 to seg31 ?? 15 k w lcd leak current i lcdl v0 to v3, com0 to com3, seg0 to seg31 ??? 5 m a
mb89550a series 32 (continued) parameter sym- bol pin name condition value unit remarks min typ max lcd step-up output voltage v ov3 v3 v1 = 1.5 v ? 4.5 ? v models with step-up circuits only v ov2 v2 ? 3.0 ? v reference voltage input impedance r rin v1 ? 600 1000 1400 k w models with step-up circuits only input capacitance c in pins other than v cc ,v ss f ch = 1 mhz ? 10 ? pf v1 input voltage v i1 v1 i in = 0 m a ? 1.5 ? v models with step-up circuits only
mb89550a series 33 4. ac characteristics (1) reset timing (dvr = v cc1 = 3 v, avss = vss = 0 v, t a = - 40 c to + 85 c) note : t hcly is the main clock oscillator period. (2) power-on reset (avss = vss = 0 v, t a = - 40 c to + 85 c) note : be sure that the power supply rise time is less than the selected oscillator stabilization period. also, when varying the supply voltage during operation, it is recommended that the supply voltage be increased gradually. parameter symbol confition rating unit remarks min max rst l pulse width t zlzh ? 48 t hcly ? ns parameter symbol confition rating unit remarks min max power supply rise time t r ? 0.05 50 ms power supply cutoff time t off 1 ? ms for repeated operation rst 0.2 v cc 0.2 v cc t zlzh v cc1, v cc2 t r 1.8 v 0.2 v 0.2 v 0.2 v t off on the mb89pv550a and mb89548a oscillation begins and the power-on reset is applied on the rise of the v cc2 .on the mb89558a and MB89557A, oscillation begins and the power-on reset is applied on the rise of the v cc1 .
mb89550a series 34 (3) power supply voltage (4) clock timing (avss = vss = 0 v, t a = - 40 c to + 85 c) parameter symbol pin name condi- tion value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 12.5 mhz f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 80 ? 1000 ns t lcyl x0a, x1a ? 30.5 ?m s input clock pulse width p wh1 p wl1 x0 20 ?? ns external clock p wh2 p wl2 x0a ? 15.2 ?m s external clock input clock rise, fall time t cr t cf x0 ?? 10 ns external clock 0 v v cc2 v cc1 be sure that the power supply is set so that v cc2 3 v cc1 . the mb89pv550a and mb89p558a operate on the v cc2 power supply only. on the mb89558a and MB89557A, v cc1 is the power supply for internal cpu operation, and v cc2 is the i/o power supply.
mb89550a series 35 x0 and x1 clock timing and input conditions clock configurations t cr t cf 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc x0 p wh1 p wl1 t hcyl x0 x1 c1 c2 f ch f ch x0 x1 when using a crystal oscillator or ceramic oscillator when using an external clock open
mb89550a series 36 (5) instruction cycle (avss = vss = 0 v, t a = - 40 c to + 85 c) note : instruction execution time settings differ for 12.5 mhz operation. parameter sym- bol value unit remarks instruction cycle (minimum instruction execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch , m s operating at f ch = 12.5 mhz (4/f ch ) t inst = 0.32 m s 2/f cl m s operating at f cl = 32.768 khz t inst = 61.036 m s x0a and x1a clock timing conditions clock configurations t cr t cf 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc x0a p wh2 p wl2 t lcyl x0a x1a x0a x1a c1 c2 f cl f cl when using a crystal oscillator or ceramic oscillator when using an external clock open
mb89550a series 37 (6) serial i/o timing (v cc1 = 3.0 v, av cc = avr = dvr = v cc2 = 5 v, avss = vss = 0 v, t a = - 40 c to + 85 c) * : for a definition of t inst see (5) instruction cycle. parameter sym- bol pin nme condition value unit remarks min max serial clock cycle time t scyc sck, uck internal clock operation 2 t inst * ?m s sck ? so time uck ? uo time t slov sck, so, uck, uo - 200 + 200 ns valid si ? sck - valid ui ? uck - t ivsh si, sck 1/2 t inst * ?m s sck -? valid si hold time uck -? valid ui hold time t shix sck, si, uck, ui 1/2 t inst * ?m s serial clock h pulse width t shsl sck, uck external clock operation 1 t inst * ?m s serial clock l pulse width t slsh 1 t inst * ?m s sck ? so time uck ? uo time t slov sck, so, uck, uo 0200ns valid si ? sck - valid ui ? uck - t ivsh si, sck, ui, uck 1/2 t inst * ?m s sck -? valid si hold time uck -? valid ui hold time t shix sck, si, uck, ui 1/2 t inst * ?m s internal shift clock mode external shift clock mode sck uck so uo si ui t scyc t ivsh t slov t shix 0.8 v 0.8 v 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 2.4 v sck uck so uo si ui t slsh t shsl t ivsh t slov t shix 0.2 v cc 0.8 v 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc
mb89550a series 38 (7) peripheral input timing (v cc1 = 3 v, av cc = avr = dvr = v cc2 = 5.0 v, avss = vss = 0 v, t a = - 40 c to + 85 c) * : for a definition of t inst see (5) instruction cycle. parameter symbol pin nme condition value unit remarks min max peripheral input h level pulse width 1 t ilih1 ec1, ec2, ec3 int10 to int17 ? 1 t inst * ?m s peripheral input l level pulse width 1 t ihil1 ec1, ec2, ec3 int10 to int17 ? 1 t inst * ?m s peripheral input h level pulse width 1 t ilih2 pwc, int20 to int27 ? 2 t inst * ?m s peripheral input l level pulse width 1 t ihil2 pwc, int20 to int27 ? 2 t inst * ?m s ec1, ec2, ec3 int10 ~ int17 int20 ~ int27, pwc t ihil1 t ilih1 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t ihil2 t ilih2 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc
mb89550a series 39 (8) electrical characteristics for the a/d converter (v cc1 = 3 v, av cc = avr = dvr = v cc2 = 3.5 v to 5.5 v, av ss = v ss = 0 v, t a = - 40 c to + 85 c) * : includes sampling time. (9) electrical characteristics for the d/a converter (v cc1 = 3 v, av cc = avr = dvr = v cc2 = 3.5 v to 5.5 v, av ss = v ss = 0 v, t a = - 40 c to + 85 c) *1 : with load capacitance 20 pf. *2 : no-load conversion *3 : stop mode item sym- bol pin nme condition rating unit remarks min typ max resolution ?? ?? 10 ? bit total error avr = av cc ?? 5.0 lsb linearity error ?? 2.5 lsb differential linearity error ?? 1.9 lsb zero transition voltage v ot an0 to an7 av ss - 3.5 + 0.5 av ss + 4.5 lsb full scale transition voltage v fst avr - 6.5 avr - 1.5 avr + 1.5 lsb variation between channels ? ?? 4lsb conversion time ? ? ? 60 tinst ?m s* sampling time ? 16 tinst ?m s analog input current i ain an0 to an7 ?? 10 m a analog input voltage v ain av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v reference voltage supply current i r a/d operating ? 400 ?m a i rh a/d stop ?? 5 m a item sym- bol pin nme condition rating unit remarks min typ max resolution ? ? ?? 8 ? bit differential linearity error avr = av cc ?? 0.9 lsb linearity error ?? 1.5 lsb conversion time ? 10 20 m s*1 analog reference voltage dvr v ss + 3.0 ? av cc v reference voltage supply current i dvr d/a running ? 120 300 m a*2 i dvrs d/a off ?? 10 m a*3 analog output impedance ?? ? ? 20 ? k w mb89p558a ? 30 ? k w mb89558a/ 557a
mb89550a series 40 (10) a/d converter glossary resolution the level of analog variation that can be recognized by the a/d converter. linearity error (unit : lsb) the deviation between the actual conversion characteristics and the line linking the zero transition point (00 0000 0000 ?? 00 0000 0001) and the full-scale transition point (11 1111 1110 ?? 11 1111 1111) . differential linearity error (unit : lsb) the variation from the theoretical input voltage required to change the output code by 1 lsb. total error (unit : lsb) the total error is the difference between the actual value and the theoretical value. (continued) v fst 1.5 lsb 1 lsb 0.5 lsb v ot avr av ss 3ff 3fe 3fd 004 003 002 001 v nt (1 lsb n + 0.5 lsb) avr av ss 3ff 3fe 3fd 004 003 002 001 theoretical i/o characteristics analog input digital output 1 lsb = v fst - v ot 1022 (v) total error analog input digital output total error for digital output n = v nt - {1 lsb n + 0.5 lsb} 1 lsb actual conversion characteristic actual conversion characteristic theoretical characteristic
mb89550a series 41 (continued) 004 003 002 001 av ss 3ff 3fe 3fd 3fc avr 3ff 3fe 3fd 004 003 002 001 av ss avr v nt (1 lsb n + v ot ) v fst (actual measured value) v (n + 1) t v nt n + 1 n n - 1 n - 2 av ss avr zero transition error analog input full-scale transition error digital output digital output linearity error analog input differential linearity error analog input digital output digital output - 1 differential linearity errorin digital output n v ( n + 1 ) t - v nt 1 lsb actual conversion characteristic actual conversion characteristics v ot (actual measured value) actual conversion characteristics v fst (actual measured value) actual conversion characteristics actual conversion characteristics v ot (actual measured value) theoretical characteristic actual conversion characteristics actual conversion characteristic theoretical characteristic actual conversion characteristic linearity error in digital output n v nt - {1 lsb n + v ot } 1 lsb theoretical characteristic = = analog input
mb89550a series 42 (11) notes for a/d conversion analog input pins and input impedance the a/d converter in the mb89550a series incorporates a sample & hold circuit as shown below. when an a/ d conversion starts, the voltage at the analog input pin is captured by the sample & hold capacitor for a period of 16 instruction cycles. accordingly, if the output impedance of the external circuit connected to the analog input is high, the analog input voltage may not stabilize within the period of the analog input sampling time. therefore, it is recommended that the output impedance of the external circuit be sufficiently low (10 k w or less) . error the relative error increases as avr - av ss becomes smaller. equivalent circuit for mb89558a and MB89557A analog input c = 30 pf r = 3.2 k w analog input pin sample & hold circuit compara- tor closed for approximately 16 instruction cycles after start of a/d conversion analog channel selector equivalent circuit for mb89p558a and mb89pv550a analog input c = 64 pf r = 1.4 k w analog input pin sample & hold circuit compara- tor closed for approximately 16 instruction cycles after start of a/d conversion analog channel selector
mb89550a series 43 n n n n example characteristics (1) power supply current (external clock) (2) h level input voltage/l level input voltage (cmos input) (3) h level input voltage/l level input voltage (hysteresis input) 134 v cc1 [v] i cc - v cc1 0 10 8 6 4 2 i cc [ma] 5 2 (t a = + 25 c) 134 v cc1 [v] i ccs - v cc1 0 10 8 6 4 2 i ccs [ma] 5 2 (t a = + 25 c) f c = 12.5 mhz, 4 division f c = 10 mhz, 64 division f c = 12.5 mhz, 4 division f c = 10 mhz, 64 division v in - v cc2 0 4 3 2 1 v in [v] (t a = + 25 c) v cc2 [v] 2 45 6 3 7 v in - v cc2 0 4 3 2 1 v in [v] (t a = + 25 c) v cc2 [v] 2 45 6 3 7 v ihs v ils
mb89550a series 44 (4) pull-up resistance (5) h level output voltage (6) l level output voltage r pull - v cc2 1 1000 100 10 pull-up [k w ] (t a = + 25 c) v cc2 [v] 2 4 5 6 3 7 v oh1 - i oh 4.6 4.0 3.4 v oh1 [v] (v cc2 = 4.5 v, t a = + 25 c) i oh [ma] 0- 4 - 6 - 8 - 2 - 10 3.0 3.2 3.6 3.8 4.2 4.4 v oh2 - i oh 4.6 4.0 v oh2 [v] (v cc2 = 4.5 v, t a = + 25 c) i oh [ma] 0 - 10 - 15 - 20 - 5 - 25 3.8 4.2 4.4 v ol1 - i ol 0.8 0.2 v ol1 [v] (v cc2 = 4.5 v, t a = + 25 c) i ol [ma] 0 4 6 8 2 10 0.0 0.4 0.6 1.0 v ol2 - i ol 0.8 0.2 v ol2 [v] (v cc2 = 4.5 v, t a = + 25 c) i ol [ma] 0 10 15 20 525 0.0 0.4 0.6 1.0
mb89550a series 45 (7) a/d converter characteristic example 0 100 200 300 400 500 600 700 800 900 1000 - 2.5 - 2.0 - 1.5 - 1.0 - 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - 3.0 (v cc2 = 5.0 v, f c = 12.5 mhz, t a = + 25 ?c) liniarity error conversion characteristics error (lsb) 0 100 200 300 400 500 600 700 800 900 1000 - 2.5 - 2.0 - 1.5 - 1.0 - 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - 3.0 (v cc2 = 5.0 v, f c = 12.5 mhz, t a = + 25 ?c) differential liniarity error conversion characteristics error (lsb)
mb89550a series 46 n n n n mask options *1 : this selection determines whether pins p66, p67, p70-p77 are used as i/o ports or as segment output pins. if they are used as ports, then seg22-seg31 (nch open drain) are not restricted by the condition for input voltage to pins (v in ), namely that v in must be lower than the voltage at the v3 pin. *2 : this represents the initial value of the oscillator stabilization period select bit (sycc : wt1, wt0) of the system clock control register. no. part no. MB89557A mb89558a mb89p558a mb89pv550a specifying procedure specify when ordering mask specify at time of order specify at time of order 1 lcd drive power supply built-in step-up circuit built-in multiplier resistance (for external connection) selectable -201 built-in multiplier resistance -201 built-in multiplier resistance -202 built-in step-up circuit -202 built-in step-up circuit -203 built-in step-up circuit -203 built-in step-up circuit 2 port/segment selection* 1 p66 (seg22) , p67 (seg23) , p70 (seg24) , p71 (seg25) , p72 (seg26) , p73 (seg27) , p74 (seg28) , p75 (seg29) , p76 (seg30) , p77 (seg31) selectable -201 segment selected (seg22-seg31 selected) -201 segment selected (seg22-seg31 selected) -202 segment selected (seg22-seg31 selected) -202 segment selected (seg22-seg31 selected) -203 port selected (p66, p67, p70-p77 selected) -203 port selected (p66, p67, p70-p77 selected) 3 main clock initial value* 2 selection for os- cillator stabilization wait period (fch = 12.5 mhz) 01 : 2 14 /fch (approx. 1.31 ms) 10 : 2 17 /fch (approx. 10.48 ms) 11 : 2 18 /fch (approx. 20.97 ms) selectable 2 18 /fch (approx. 20.97 ms) 2 18 /fch (approx. 20.97 ms)
mb89550a series 47 n n n n ordering information part no. package remarks mb89558apfv-xxx 100-pin plastic lqfp (fpt-100p-m05) mb89558apft-xxx 100-pin plastic tqfp (fpt-100p-m18) mb89p558a-201pfv versions without step-up mb89p558a-202pfv with step-up 32 segment mb89p558a-203pfv with step-up 22 segment 100-pin plastic lqfp (fpt-100p-m05) mb89p558a-201pft versions without step-up mb89p558a-202pft with step-up 32 segment mb89p558a-203pft with step-up 22 segment 100-pin plastic tqfp (fpt-100p-m18) mb89pv550a-201cf versions without step-up mb89pv550a-202cf with step-up 32segment mb89pv550a-203cf with step-up 22segment 100-pin ceramic mqfp (mqp-100c-p02)
mb89550a series 48 n n n n package dimensions (continued) 100-pin plasic lqfp (fpt-100p-m05) note) pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2000 fujitsu limited f100007s-3c-5 14.00?.10(.551?004)sq 16.00?.20(.630?008)sq 125 26 51 76 50 75 100 0.50(.020) 0.20?.05 (.008?002) m 0.08(.003) 0.145?.055 (.0057?0022) 0.08(.003) "a" index .059 ?004 +.008 ?.10 +0.20 1.50 (mounting height) 0?8 0.50?.20 (.020?008) 0.60?.15 (.024?006) 0.25(.010) 0.10?.10 (.004?004) details of "a" part (stand off)
mb89550a series 49 (continued) 100-pin plasic tqfp (fpt-100p-m18) note) pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2000 fujitsu limited f100029s-c-2-3 index 12.000.10(.472.004)sq 14.000.20(.551.008)sq "a" 0.1450.055 (.006.002) 51 75 50 76 26 100 1 lead no. 25 0.40(.016) 0.180.05 (.007.002) 0.07(.002) m 0 ~ 8 0.25(.010) 0.600.15 (.024.006) 0.100.05 (.004.002) (stand off) details of "a" part 0.08(.003) (.043.004) 1.100.10
mb89550a series 50 (continued) 100-pin ceramic mqfp (mqp-100c-p02) dimensions in mm (inches) c 1994 fujitsu limited m100002sc-2-2 14.82?.35 (.583?014) 15.00?.25 (.591?010) pin no.1 index 1.02?.13 (.040?005) 7.14(.281) typ pad no.1 index 0.15?.05 (.006?002) 9.94(.392)max 1.10 +0.45 ?.25 +.018 ?010 .043 10.92(.430) typ 4.50(.177)sq typ 12.00(.472)typ 17.20(.667)typ 12.00(.472) typ 17.20(.667) typ 0.18?.05 (.007?002) 0.50?.15 (.0197?0060) 0.30(.012) typ 10.92(.430) typ sq sq
mb89550a series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0205 ? fujitsu limited printed in japan

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